1. Field of the Invention
The present invention is generally directed to semiconductor processing, and, more particularly, to a method of controlling junction recesses in a semiconductor device.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, the size of many components of a typical field effect transistor, e.g., channel length, source/drain junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Modern integrated circuit devices are comprised of millions of transistors formed above a semiconducting substrate. In order to perform their intended function, the various semiconductor devices, e.g., transistors, must be electrically coupled to one another. In most modern integrated circuit devices this is accomplished by forming a plurality of conductive interconnections, i.e., conductive lines and conductive plugs, above the substrate. Typically, these conductive lines and conductive plugs are formed in alternating layers above the substrate. Such conductive interconnections allow signals to propagate throughout the integrated circuit device thereby enabling the device to perform its intended function.
By way of background, FIG. 1 depicts an illustrative transistor 10 for purposes of explaining one or more problems that may be solved or reduced by the present invention. As shown in FIG. 1, the transistor 10 is formed in an active area 12 that is defined in the semiconducting substrate 14 by isolation structures 16 formed therein. The transistor 10 is comprised of a gate insulation layer 18, a gate electrode 20, a sidewall spacer 24, and a plurality of source/drain regions 28. The transistor 10 is also comprised of metal silicide layers 29 formed above the source/drain regions 28 and the gate electrode 20. All of the various components of the transistor 10 depicted in FIG. 1 may be formed using a variety of known processing techniques and they may be comprised of a variety of materials. For example, the gate insulation layer 18 may be comprised of a thermally grown layer of silicon dioxide, the gate electrode 20 may be comprised of polysilicon, the sidewall spacer 24 may be comprised of silicon dioxide, and the metal silicide regions 29 may be comprised of, for example, cobalt silicide or titanium silicide.
Also depicted in FIG. 1 is a conductive interconnection 11 formed above one of the source/drain regions 28 of the transistor 10. Please note that, for purposes of clarity and explanation, only one such conductive interconnection 11 is depicted in FIG. 1, although such a conductive interconnection will be applied to both of the source/drain regions 28, as well as the gate electrode 20. The conductive interconnection 11 may take a variety of forms, e.g., a strap that would extend over the isolation region 16 to connect to another source/drain region (not shown) of a separate transistor (not shown). Alternatively, the conductive interconnection 11 may extend vertically upward to additional conductive interconnections, e.g., a conductive line formed on the integrated circuit device. Moreover, the conductive interconnection 11 may take a variety of shapes or forms, e.g., straps or generally cylindrical contacts, that may have an oval or circular cross-sectional configuration when viewed from above, etc.
The isolation structure 16 is typically comprised of an insulating material, such as silicon dioxide, or other like material. The isolation structure 16 may be constructed by forming a trench in the substrate 14, filling the trench with an appropriate insulating material, e.g., silicon dioxide, and, thereafter, performing a chemical mechanical polishing operation to remove any excess material.
After the isolation structure 16 is formed, many additional processing steps must be performed to form the transistor 10. Those process steps, at times, tend to erode or consume portions of the isolation structure 16, particularly at the interface between the source/drain region 28 and the isolation structure 16, thereby resulting in the recess 25 depicted in FIG. 1. There are a vast variety of process steps that may cause erosion of the isolation structures 16. For example, the surface of the substrate 14 is frequently cleaned to remove native oxides, and the sidewall spacers 24 are formed by depositing a layer of material, e.g., silicon dioxide, and, thereafter, performing an etching process, etc. Of course, as those skilled in the art will recognize, the recess 25 depicted in FIG. 1 is only schematic in nature, i.e., any such recess may take a variety of shapes. The depth and extent of the recess 25 may also vary.
Undesirable consumption of the isolation structure may also occur when conductive interconnections, such as the conductive interconnection 11, are formed above the source/drain regions 28. In some situations, the conductive interconnection 11 would ideally be positioned entirely over the source/drain region 28, i.e., it will be located between the isolation structure 16 and the sidewall spacer 24. Such a conductive interconnection, such as a generally cylindrical conductive contact (not shown), may be formed by forming a layer of insulating material, and, thereafter, performing one or more etching processes to define an opening in the insulating layer where the conductive contact will be formed. However, in situations where the opening in the insulating layer is misaligned, i.e., where the opening extends over a portion of the isolation structure 16, the isolation structure 16 may be subjected to the etching process that is used to form the opening in the insulation layer.
As a result of all of these various process steps, portions of the isolation structure 16 may be consumed or eroded away to form the recess 25 that exposes a portion of the sidewall 27 of the source/drain region 28. This recess 25 allows the conductive interconnection 11 to be formed on the exposed surface 27 of the source/drain region 28, thereby effectively reducing the junction depth of the device in that local area. As a result, the device may exhibit increased off-state leakage currents and increased power consumption, both of which are undesirable characteristics in modern integrated circuit devices.
The present invention is directed to a method that solves or reduces some or all of the aforementioned problems.
The present invention is directed to a method of forming a transistor. In one illustrative embodiment, the method comprises providing a substrate that is doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implantation process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.